Title page for ETD etd-01102009-063025
|Type of Document
||Behavioral testbench development for DSP models
||Master of Science
|Armstrong, James R.
|Cyre, Walling R.
|Gray, Festus Gail
|Date of Defense
Generation of testbenches for large DSP behavioral models is a complicated, labor
intensive task. Also, tests generated manually satisfy no formal definition of completeness.
To address these needs, high level approaches to test bench development are employed
which relieve the modeler of the details of test bench development.
Two basic approaches that are used currently for testbench development are behavioral
and structural testbench development. This thesis concentrates on the development of a
methodology for modeling a set of behavioral testbenches. Here, a CASE tool, I-Logix
Express V-HDL, is used to model state-machine as well as data flow behavior of the
testbench and then dump the corresponding VHDL code automatically. Two approaches
are followed for the generation of data values for the inputs to the testbenches: 1) File I/O
and 2) User interaction. This thesis also describes the development of an intelligent user
interface (in C) which prompts the user for the input data values and combines this
information with the testbench code. The intelligent interface also allows the user to
specify and control file I/O as a data source. As an implementation of this methodology,
testbenches for the following two DSP applications have been developed and are
described here : 1) Infra-Red Search and Track algorithm and 2) Synthetic Aperture
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