Title page for ETD etd-01102009-063929


Type of Document Master's Thesis
Author Harper, Scott Jeffery
URN etd-01102009-063929
Title Design of a hardware interface for a high-speed parallel network
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
Midkiff, Scott F. Committee Chair
Davis, Nathaniel J. IV Committee Member
Jacobs, Ira Committee Member
Keywords
  • Computer interfaces
Date of Defense 1994-08-15
Availability restricted
Abstract

Parallelism can use existing technology in computer communications network design to provide higher data rates and a greater degree of flexibility than monolithic systems. This research investigates the design of a high-speed Parallel Local Area Network (PLAN) interface. It defines the goals of a PLAN interface as low data latency, high data throughput, scalability, and low cost. Three fundamental PLAN interface categories are proposed to meet these goals. These categories are single-bus, dual-bus, and bus-free adaptors. The relative merits of each category are discussed in terms of suitability to several adaptor applications. Each category is further explored by developing a VHDL model of a representative system. The latency, throughput, and component utilization of each model is measured. For medium to large data sets, the dual-bus design provides slightly greater throughput when transmitting encoded data. When transmitting medium to large unencoded data sets, the bus-free design yields marginally higher throughput. In nearly all cases the bus-free design has a greater latency than either of the bus-based design options. Other insights gained from the models regarding physical construction of each adaptor type are also presented.

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