

Type of Document Master's Thesis Author Hendry, James Hugh URN etd-01122004-151832 Title The Effects of Caching on Reconfigurable Adaptive Computing Systems Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Mark T. Jones Committee Chair James R. Armstrong Committee Member Peter M. Athanas Committee Member Keywords
- Configurable Computing
- FPGA
- Adaptive Computing
- Run-Time Reconfiguration
Date of Defense 2003-12-19 Availability unrestricted Abstract Adaptive computing systems have proven useful for implementing awide range of algorithms. A limitation of current systems is the
relatively small amount of reconfigurable hardware resources. Many
algorithms require more hardware resources than are available.
One solution to this problem is runtime reconfiguration
(RTR). Using RTR techniques, a large algorithm is implemented as a
collection of configurations for the reconfigurable hardware. These
configurations are loaded onto the reconfigurable hardware as
necessary to implement the algorithm. A primary limitation of RTR is
that the reconfiguration process is slow. Therefore, methods of
decreasing reconfiguration time are desirable.
Another method of implementing large algorithms on small hardware is
to use multiple configurable computing platforms connected via a
communication network. RTR techniques can be used in conjunction with
this method to further increase hardware availability. In this case
reconfiguration time is increased by the overhead of transmitting data
across the communication network. Methods of decreasing network
overhead are desirable.
This thesis discusses the use of caching techniques to decrease
reconfiguration time. An architecture for caching configurations is
implemented on a
configurable computing system platform. The use of caching to
decrease network overhead is discussed and exhibited. An example
application is
implemented and used to evaluate the effects of caching on
reconfiguration time and algorithm performance.
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