Title page for ETD etd-01172009-055053


Type of Document Master's Thesis
Author Wood, Joseph Lee
Author's Email Address jowood4@vt.edu
URN etd-01172009-055053
Title Three-Dimensional Heterogeneous Integration for RF/Microwave Applications
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Raman, Sanjay Committee Chair
Agah, Masoud Committee Member
Hendricks, Robert W. Committee Member
Keywords
  • mm-wave
  • Integration
  • interconnect
  • vertical
  • coplanar waveguide
  • heterogeneous
  • liquid metal
Date of Defense 2008-09-11
Availability unrestricted
Abstract
High performance RF/mixed signal systems require new interconnect strategies to combine high frequency (microwave/mm-wave) circuitry with silicon mixed-signal and baseband digital processing. In such systems, heterogeneous vertical integration, in which circuits in different technologies can be stacked on top of each other within the system architecture, can reduce the overall system size and power consumption. Chip stacking also enables optimally-performing heterogeneous systems, because each level of the stack can consist of components fabricated in their most suited device or substrate technology. Two novel approaches for the vertical interconnection of heterogeneous integrated systems are proposed in this work. These approaches are related to flip-chip bonding techniques used in Radio-Frequency (RF)/microwave integrated circuits.

The first proposed approach involves an interlocking mechanical structure that supports flip-chip assembled Monolithic Microwave Integrated Circuits (MMICs). Photolithographically patterned thick-film SU-8 structures are applied to both the chip and the carrier such that the chip self-aligns into place and mates with the carrier. Gold bumps embedded within the structures electrically connect the chip pads to the carrier pads. This method is demonstrated through the assembly of a SiGe power amplifier MMIC onto a high resistivity silicon carrier.

The second proposed approach involves vertical interconnects consisting of room temperature liquid-state metals. The fluid nature of the liquid bumps allows them to be robust in the presence of thermo-mechanical stresses, such as Coefficient of Thermal Expansion (CTE) mismatch between the interconnected chips. SU-8 structures are used to form a shaping mold on the bottom carrier that contains the liquid metal. Gold posts are electroplated on the top chip, then mated with the SU-8 mold, thereby making contact with the liquid metal to form the electrical continuity.

For each of these proposed methods, design and fabrication considerations are discussed in detail. RF measurements on prototype structures up to Ka band are performed to verify the functionality of the proposed methods. Given the results of these proof-of-concept efforts, electrical characteristics of the materials used in these methods are determined, and recommendations are provided for future improvements and refinements to these two techniques.

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