Type of Document Master's Thesis Author Kottapalli, Sailesh URN etd-01312009-063203 Title A test plan driven test bench generation system Degree Master of Science Department Electrical Engineering Advisory Committee
Advisor Name Title Armstrong, James R. Committee Chair Cyre, Walling R. Committee Member Gray, Festus Gail Committee Member Keywords
- DSP models
Date of Defense 1996-05-05 Availability restricted Abstract
Testing and verification of large DSP models is a laborious and time consuming task. Test benches provide a platform for testing VHDL models. Development of good test benches is very critical in reducing the time, manpower and costs involved in testing of such models. Sometimes the development of test benches alone does not make the task of testing easy. High level approaches have to be developed to configure the test bench according to the required testing strategy. This would relieve the user of familiarizing himself with the details of the models to configure the test bench properly for a particular testing scenario.
A test plan organizes the system requirements in ternlS of how these requirements will be tested. It divides the system requirements into groups and allocates a set of tests to each of the requirements groups. The main emphasis of this thesis is to develop an approach to interface a test bench with a test plan, which configures the test bench according to the test to be performed.
As an illustration of this approach a test plan interface was developed for a test bench system for an Infrared Search and Track (IRST) algorithm. A requirements interface was designed to convert the primary paranleters to the form required by the test bench primitives. Enhancements were made to the previous version of the test bench primitives and a structural test bench was developed by the interconnection of the test bench primitives using a commercial schematic capture tool, Synopsys Graphical Environment (SGE). A test plan interface was designed to configure the test bench with the required input parameters for creation of test vectors according to the test plan. The test bench can be operated in iterative mode to find the limiting value of a system parameter.
This thesis also describes the integration of the different elements of the test bench, developed using different computer tools, and programming languages into a single test bench generation system. A menu driven X-Windows user interface was also developed to facilitate easy operation of the test bench generation system.
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