Type of Document	Master's Thesis
Author	Gupta, Puneet
Author's Email Address	pugupta@vt.edu
URN	etd-02202004-214315
Title	High Quality Transition and Small Delay Fault ATPG
Degree	Master of Science
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Michael S, Hsiao Committee Chair Ha, Dong Sam Committee Member Shukla, Sandeep K. Committee Member
Keywords	Non-Robust Paths Robust Paths Delay Testing Transition Faults
Date of Defense	2004-02-13
Availability	unrestricted
Abstract Path selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture small-distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. To deal with small delay faults, we have proposed a new transition fault model called As late As Possible Transition Fault (ALAPTF) Model. The model aims at detecting smaller delays, which will be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, simple path-delay model will miss such faults. The algorithm proposed also detects robust and non-robust paths along with the transition faults and the execution time is linear to the circuit size. Results on ISCAS’85 and ISCAS’89 benchmark circuits shows that for all the cases, the new model is capable of detecting smaller gate delays and produces better results in case of process variations. Results also show that the filtered non-robust path set can be reduced to 40% smaller than the conventional path set without losing delay defect coverage.
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