Title page for ETD etd-030199-155102


Type of Document Master's Thesis
Author Stinnett, William A.
Author's Email Address wstinnet@ford.com
URN etd-030199-155102
Title Thermal Management of Power Electronic Building Blocks
Degree Master of Science
Department Mechanical Engineering
Advisory Committee
Advisor Name Title
Nelson, Douglas J. Committee Chair
Dancey, Clinton L. Committee Member
Elshabini-Riad, Aicha A. Committee Member
Keywords
  • PEBB
  • Thermal Management
  • Power Electronics
  • MCM
Date of Defense 1999-02-10
Availability unrestricted
Abstract
Development of Power Electronic Building Block (PEBB) modules, initiated through the Office of Naval Research (ONR), is a promising enabling technology which will promote future electrical power systems. Key in this development is the thermal design of a PEBB packaging scheme that will manage the module's high heat dissipation levels. As temperatures in electronics are closely associated with operating efficiency and failure rates, management of thermal loads is necessary to ensure proper and reliable device performance.

The current work investigates the thermal design requirements for a preliminary PEBB module developed by the NSF Center for Power Electronics Systems (CPES) at Virginia Tech. This module locates four primary heat-generating devices onto a copper bonded substrate in a multi-chip module format. The thermal impact of several design variables (including heat sink quality, substrate material, device spacing, and substrate and metallization thickness) are modeled within the multi-layer thermal analysis software TAMSä. Model results are in the form of metal layer surface temperatures that closely represent the device junction temperatures. Other design constraints such as electrical and material characteristics are also considered in the thermal design.

Design results indicate for the device heat dissipation levels that a low resistance heat sink coupled with a high conductivity substrate, such as aluminum nitride, are required for acceptable device junction temperatures. Substrate performance, in the form of a spreading resistance component, will be negatively affected by a lower quality heat sink. Both forced air and cold plate cooling methods were found acceptable; factors such as environment, cost and integration will determine which solution is most feasible. Maximum surface temperatures can be lowered somewhat through adjustment of device spacing. However, this reduction was small compared to the impact on parasitic capacitance. Additionally, there is some thermal benefit to thicker high-conductivity substrates, whereas lower conductivity substrates will increase the maximum surface temperature. Thicker copper layers will prove beneficial though this benefit is not as great for higher conductivity substrates.

Also discussed are the on-going and future development efforts that are expected to require thermal consideration. These consist of a top-level thermal bus for additional heat removal, the use of metal matrix composites and concepts for multi-module integration.

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