Type of Document Master's Thesis Author Lai, Pengjie Author's Email Address email@example.com URN etd-03042010-163902 Title Improvement of Sigma Voltage Regulator - A New Power Architecture Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Lee, Fred C. Committee Chair Lindner, Douglas K. Committee Member Wang, Fei Fred Committee Member Keywords
- Output Impedance Design
- Unregulated DCX
- Sigma Voltage Regulator
Date of Defense 2010-02-19 Availability unrestricted AbstractWith lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard.
Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design.
To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called “Sigma” architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept.
The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor.
This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a “non-obstacle” path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective.
In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for future’s lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved.
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