Title page for ETD etd-03132001-140635


Type of Document Master's Thesis
Author Richmond II, Richard Steven
Author's Email Address srichmond@vt.edu
URN etd-03132001-140635
Title A Low-Power Design of Motion Estimation Blocks for Low Bit-Rate Wireless Video Communications
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Ha, Dong Sam Committee Chair
Armstrong, James R. Committee Member
Reed, Jeffrey Hugh Committee Member
Keywords
  • Four-step search
  • Low power
  • Motion estimation
  • H.263
Date of Defense 2001-03-13
Availability unrestricted
Abstract
Motion estimation and motion compensation comprise one of the most important compression methods for video communications. We propose a low-power design of a motion estimation block for a low bit-rate video codec standard H.263. Since the motion estimation is computationally intensive to result in large power consumption, a low-power design is essential for portable or mobile systems. Our block employs the Four-Step Search (4SS) method as its primary algorithm. The design and the algorithm have been optimized to provide adequate results for low-quality video at low-power consumption. The model is developed in VHDL and synthesized using a 0.35 um CMOS library. Power consumption of both gate-level circuits and memory-accesses have been considered. Gate-level simulation shows the proposed design offers a 38% power reduction over a "baseline" implementation of a 4SS model and a 60% power reduction over a baseline Three-Step Search (TSS) model. Power savings through reduction of memory access is 26% over the TSS model and 32% over the 4SS model. The total power consumption of the proposed motion estimation block ranges from 7 - 9 mW and is dependent on the type of video being motion estimated.
Files
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  Final.pdf 721.35 Kb 00:03:20 00:01:43 00:01:30 00:00:45 00:00:03

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