The Rapid Prototyping of Application Specific Signal Processors (RASSP) program
seeks an improvement in the time required to take a design from concept to fielded
prototype or to upgrade an existing design, with similar improvements in design quality
and life cycle cost. The term Rapid System Prototyping signifies the need to develop
systems in significantly less time or with significantly less effort, and thus provides a
solution to the main problem facing the design community. Entire systems are
synthesized from models in hardware description languages (HDLs).
The goal of this thesis is to provide a methodology for rapidly creating a database, that
can be reused thus decreasing design cost and time for both current and future projects.
To demonstrate the methodology, this thesis describes the development of VHDL
primitives supporting digital signal processing (DSP) and image processing operations for
two of the RASSP specific applications: 1) Synthetic aperture radar image processor
(SAR) and 2) Automatic target recognition (ATR) image processing algorithm. Different
techniques are investigated to populate these VHDL libraries using commercial tools.
The thesis proposes techniques for solving some problems related to the use of
commercial tools to generate VHDL code. It includes a full implementation of the SAR
processor algorithm developed from DSP primitives.
next to an author's name indicates that all files or directories associated with their ETD are accessible from the Virginia Tech campus network only.
![[VT]](http://scholar.lib.vt.edu/images/ETD-db/restricted.gif)
