Title page for ETD etd-04102012-140020


Type of Document Master's Thesis
Author Rafeei, Lalleh
Author's Email Address lrafeei@vt.edu
URN etd-04102012-140020
Title Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Nazhandali, Leyla Committee Chair
Meehan, Kathleen Committee Member
Shukla, Sandeep K. Committee Member
Keywords
  • subthreshold
  • approximation framework
  • power
  • timing
  • CMOS
  • VLSI
  • Ultra-Low-Voltage
Date of Defense 2012-04-02
Availability unrestricted
Abstract
Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits.
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