Type of Document Master's Thesis Author Kothari, Rajiv D. URN etd-04182009-041213 Title Experimental results on aliasing errors in circular BIST design Degree Master of Science Department Electrical Engineering Advisory Committee
Advisor Name Title Ha, Dong Sam Committee Chair Armstrong, James R. Committee Member Midkiff, Scott F. Committee Member Keywords
- Digital electronics
Date of Defense 1991-09-15 Availability restricted Abstract
The circular BIST design is a technique in which the existing circuit is modified, so that the processes of test generation and response compaction are carried out by the circuit being tested itself. Most response compaction techniques suffer from loss of information, known as aliasing. Aliasing is said to occur in a response compaction technique when the response generated by the circuit, under the presence of a fault, is different from its fault-free response, but this information is later lost during compaction, and the faulty compacted response at the end of the test session is identical to the fault-free compacted response.
A program to synthesize circular BIST hardware on general sequential circuits has been developed. A parallel fault simulator has been developed to detect aliasing errors in circular BIST design. Experimental results on aliasing probability in circular BIST design are reported for twenty-three sequential benchmark circuits.
Filename Size Approximate Download Time (Hours:Minutes:Seconds)
28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access LD5655.V855_1991.K673.pdf 2.00 Mb 00:09:15 00:04:45 00:04:09 00:02:04 00:00:10next to an author's name indicates that all files or directories associated with their ETD are accessible from the Virginia Tech campus network only.
If you have questions or technical problems, please Contact DLA.