Title page for ETD etd-04262005-133303


Type of Document Master's Thesis
Author Francis, Gerald
Author's Email Address jerryf@vt.edu
URN etd-04262005-133303
Title A Synchronous Distributed Digital Control Architecture for High Power Converters
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Boroyevich, Dushan Committee Chair
Kachroo, Pushkin Committee Member
Tranter, William H. Committee Member
Keywords
  • Universal Controller
  • Power Electronics
  • Synchronous Communication Networks
  • Plug and Play
  • Fiber Optics
  • Digital Control Systems
  • AEPS
  • Power Electronics Building Blocks (PEBB)
  • DSP
  • FPGA
  • Electric Ship
  • Electric Drives
Date of Defense 2004-03-03
Availability unrestricted
Abstract
Power electronics applications in high power are normally large, expensive, spatially distributed systems. These systems are typically complex and have multiple functions. Due to these properties, the control algorithm and its implementation are challenging, and a different approach is needed to avoid customized solutions to every application while still having reliable sensor measurements and converter communication and control.

This thesis proposes a synchronous digital control architecture that allows for the communication and control of devices via a fiber optic communication ring using digital technology. The proposed control architecture is a multidisciplinary approach consisting of concepts from several areas of electrical engineering. A review of the state of the art is presented in Chapter 2 in the areas of power electronics, fieldbus control networks, and digital design. A universal controller is proposed as a solution to the hardware independent control of these converters. Chapter 3 discusses how the controller was specified, designed, implemented, and tested. The power level specific hardware is implemented in modules referred to as hardware managers. A design for a hardware manager was previously implemented and tested. Based on these results and experiences, an improved hardware manager is specified in Chapter 4. A fault tolerant communication protocol is specified in Chapter 5. This protocol is an improvement on a previous version of the protocol, adding benefits of improved synchronization, multimaster support, fault tolerant structure with support for hot-swapping, live insertion and removals, a variable ring structure, and a new network based clock concept for greater flexibility and control. Chapter 6 provides a system demonstration, verifying the components work in configurations involving combinations of controllers and hardware managers to form applications. Chapter 7 is the conclusion. VHDL code is included for the controller, the hardware manager, and the protocol. Schematics and manufacturing specifications are included for the controller.

Files
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  JF_THESIS_RELEASE_N.pdf 6.96 Mb 00:32:12 00:16:33 00:14:29 00:07:14 00:00:37
  UCSchematics.pdf 215.67 Kb 00:00:59 00:00:30 00:00:26 00:00:13 00:00:01

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