Title page for ETD etd-04302007-134556


Type of Document Master's Thesis
Author Yu, Pengyuan
Author's Email Address peyu1983@vt.edu
URN etd-04302007-134556
Title Implementation of DPA-Resistant Circuit for FPGA
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Schaumont, Patrick Robert Committee Chair
Hsiao, Michael S. Committee Member
Shukla, Sandeep K. Committee Member
Keywords
  • Differential Power Analysis
  • Secure Circuit
  • FPGA
Date of Defense 2007-04-24
Availability unrestricted
Abstract
In current Field-Programmable-Logic Architecture (FPGA) design flows, it is very hard to control the routing of submodules. It is thus very hard to make an identical copy of an existing circuit within the same FPGA fabric. We have solved this problem in a way that still enables us to modify the logic function of the copied submodule. Our technique has important applications in the design of side-channel resistant implementations in FPGA. Starting from an existing single-ended design, we are able to create a complementary circuit. The resulting overall circuit strongly reduces the power-consumption-dependent information leaks. We will show all the necessary steps needed to implement secure circuits on a FPGA, from initial design stage all the way to verification of the level of security through laboratory measurements. We show that the direct mapping of a secure ASIC circuit-style in an FPGA does not preserve the same level of security, unless our symmetrical routing technique is employed. We demonstrate our approach on an FPGA prototype of a cryptographic design, and show through power-measurements followed by side-channel power analysis that secure logic implemented with our approach is resistant whereas non-routing-aware directly mapped circuit can be successfully attacked.
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