| Type of Document |
Master's Thesis |
| Author |
August, Nathaniel
|
| Author's Email Address |
nate_august@hotmail.com |
| URN |
etd-05032001-111956 |
| Title |
On the Low Power Design of DCT and IDCT for Low Bit Rate Video Codecs |
| Degree |
Master of Science |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Ha, Dong Sam |
Committee Chair |
| Armstrong, James R. |
Committee Member |
| Gray, Festus Gail |
Committee Member |
|
| Keywords |
|
| Date of Defense |
2001-04-24 |
| Availability |
unrestricted |
Abstract
Wireless video systems have applications in cellular videophones, surveillance systems, and mobile patrols. The design of a wireless video system must consider two important constraints: low bit rate and low power dissipation. The ITU-T H.263 video codec standard is suitable for low bit rate wireless video systems, however it is computationally intensive. Some of the most computationally intensive operations in H.263 are the Discrete Cosine Transform (DCT) and the Inverse Discrete Cosine Transform (IDCT), which perform spatial compression and decompression of the data.
In an ASIC implementation of H.263, the high computational complexity of the DCT and IDCT leads to high power dissipation of the blocks. Low power design of the DCT and IDCT is essential in a portable wireless video system. This paper examines low power design techniques for DCT and IDCT circuits applicable for low bit rate wireless video systems. Five low power techniques are applied to baseline reference DCT and IDCT circuits. The techniques include skipping low energy DCT input, skipping all-zero IDCT input, low precision constant multipliers, clock gating, and a low transition data path. Gate-level simulations characterize the effectiveness of each technique. The combination of all techniques reduces average power dissipation by 95% over the baseline reference DCT and IDCT blocks.
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Nathaniel_August_Thesis.pdf |
510.80 Kb |
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