Title page for ETD etd-05052000-17260008


Type of Document Master's Thesis
Author Grady, Benjamin M
URN etd-05052000-17260008
Title Design and Prototyoing of a Wireless Data Transceiver in the 900MHz ISM Band
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Bostian, Charles W. Committee Chair
Pratt, Timothy J. Committee Member
Sweeney, Dennis G. Committee Member
Keywords
  • Low Cost
  • ISM Band
  • Data Radio
Date of Defense 2000-04-24
Availability unrestricted
Abstract
The Communications industry is currently involved in a wireless revolution. Consequently, there is a need for a wide variety of wireless solutions to replace existing wired systems. The major systems, such as cellular and satellite, are costly to put in place and require a low BER (bit error rate) to be successful for their real-time applications. In contrast to this are those systems that can tolerate a higher BER as a trade off for cost (<$50.00) and complexity. A typical application for these lower cost systems is monitoring non-critical data that is not required to be delivered real-time.

The work presented here focused on designing, building and testing a Proof of Concept Prototype (POCP) for a low-cost wireless data link (WDL). In a typical WDL application, problems arise when too large a data rate attempts to travel the allotted channel bandwidth in the frequency band of interest. Also, limitations imposed by current radio transceiver technology tend to limit WDL design. The existing sponsor's wired system operates at a 9600 Baud, and presented the opposite problem: the data rate was too low for the RF Microdevices RF2905 used for the POCP. This challenge necessitated the development of a low-cost encoding scheme using standard digital logic gates in place of more costly Manchester Encoding. For the digital logic encoding scheme to work, the crystal oscillators had to be modified. This resolved the problem with the low frequency limitations of the RF2905 phase locked-loop. In addition, the polled, asynchronous, and unbalanced RS485 connections of the wired system had to be adapted to interface with the single-ended data connections of the WDL. Finally, the successful design of a timing scheme, using standard TTL components and balanced to unbalanced drivers, resolved the interface problems resulting in a low-cost WDL designed to operate with an existing wired system without requiring modifications to that system. The WDL is transparent in connection and operation and can be inserted without disrupting the current wired system.

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