Type of Document Master's Thesis Author Shah, Jignesh Author's Email Address firstname.lastname@example.org URN etd-05132004-140722 Title Application Benchmarks for SCMP: Single Chip Message-Passing Computer Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Baker, James M. Jr. Committee Chair Athanas, Peter M. Committee Co-Chair Baumann, William T. Committee Co-Chair Keywords
- Parallel Computers
- Message Passing
Date of Defense 2003-08-25 Availability unrestricted AbstractAs transistor feature sizes continue to shrink, it will become feasible, and for a number of reasons more efficient, to include multiple processors on a single chip. The SCMP system being developed at Virginia Tech includes up to 64 processors on a chip, connected in a 2-D mesh. On-chip memory is included with each processor, and the architecture includes support for communication and the execution of parallel threads. As with any new computer architecture, benchmark kernels and applications are needed to
guide the design and development, as well as to quantify the system performance. This thesis presents several benchmarks that have been developed for or ported to SCMP. Discussion of the benchmark algorithms and their implementations is included, as well as an analysis of the system performance. The thesis also includes discussion of the programming environment available for developing parallel applications for SCMP.
Filename Size Approximate Download Time (Hours:Minutes:Seconds)
28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access Jignesh-Shah-Thesis-Revised-2.pdf 689.60 Kb 00:03:11 00:01:38 00:01:26 00:00:43 00:00:03
If you have questions or technical problems, please Contact DLA.