Title page for ETD etd-05152009-170830


Type of Document Master's Thesis
Author Rose, Benjamin Aaron
Author's Email Address bar234@vt.edu
URN etd-05152009-170830
Title Intra- and Inter-chip Communication Support for Asymmetric Multicore Processors with Explicitly Managed Memory Hierarchies
Degree Master of Science
Department Computer Science
Advisory Committee
Advisor Name Title
Nikolopoulos, Dimitrios S. Committee Chair
Butt, Ali R. A. Committee Member
Lowenthal, David K. Committee Member
Keywords
  • Cell BE
  • multicore
  • cluster
Date of Defense 2009-05-12
Availability unrestricted
Abstract
The use of asymmetric multi-core processors with on-chip computational

accelerators is becoming common in a variety of environments ranging from

scientific computing to enterprise applications. The focus of current research

has been on making efficient use of individual systems, and porting

applications to asymmetric processors. The use of these asymmetric processors,

like the Cell processor, in a cluster setting is the inspiration for the Cell

Connector framework presented in this thesis. Cell Connector adopts a streaming

approach for providing data to compute nodes with high computing potential but limited

memory resources. Instead of dividing very large data sets once among computation

resources, Cell Connector slices, distributes, and collects work units off of a master data

held by a single large memory machine. Using this methodology, Cell Connector is

able to maximize the use of limited resources and produces results that are up to

63.3\% better compared to standard non-streaming approaches.

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