

Type of Document Master's Thesis Author O'Neill, Michael Douglas URN etd-06122010-020415 Title An improved chip-level test generation algorithm Degree Master of Science Department Electrical Engineering Advisory Committee
Advisor Name Title No Advisors Found Keywords
- Integrated circuits
Date of Defense 1988-00-00 Availability restricted Abstract Files
Filename Size Approximate Download Time (Hours:Minutes:Seconds)
28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access LD5655.V855_1988.O645.pdf 3.11 Mb 00:14:23 00:07:24 00:06:28 00:03:14 00:00:16 next to an author's name indicates that all files or directories associated with their ETD are accessible from the Virginia Tech campus network only.
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