Type of Document	Master's Thesis
Author	Ballagh, Jonathan Bartlett
Author's Email Address	jballagh@vt.edu
URN	etd-06192001-112019
Title	An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core
Degree	Master of Science
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Dr. Peter Athanas Committee Chair Dr. Amy Bell Committee Member Dr. Cameron Patterson Committee Member Dr. Mark Jones Committee Member
Keywords	JBits Wavelets FPGA Reconfiguration
Date of Defense	2001-06-15
Availability	unrestricted
Abstract FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform. The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are presented, including speed of operation, resource consumption, and reconfiguration overhead times.
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