| Type of Document |
Master's Thesis |
| Author |
Tergino, Christian Sean
|
| Author's Email Address |
ctergino@vt.edu |
| URN |
etd-06222009-150103 |
| Title |
Efficient Binary Field Multiplication on a VLIW DSP |
| Degree |
Master of Science |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Schaumont, Patrick Robert |
Committee Chair |
| Feng, Wu-Chun |
Committee Member |
| Hsiao, Michael S. |
Committee Member |
|
| Keywords |
- Very Long Instruction Word
- Modular Multiplication
- C64x+
- Digital Signal Processor
- Multiplication
- Binary Field
- Galois Field
- GF
- Heterogeneous Multiprocessors
|
| Date of Defense |
2009-06-18 |
| Availability |
unrestricted |
Abstract
Modern public-key cryptography relies extensively on modular multiplication with long operands. We investigate the opportunities to optimize this operation in a heterogeneous multiprocessing platform such as TI OMAP3530. By migrating the long operand modular multiplication from a general-purpose ARM Cortex A8 to a specialized C64x+ VLIW DSP, we are able to exploit the XOR-Multiply instruction and the inherent parallelism of the DSP. The proposed multiplication utilizes Multi-Precision Binary Polynomial Multiplication with Unbalanced Exponent Modular Reduction. The resulting DSP implementation performs a GF(2^233) multiplication in less than 1.31us, which is over a seven times speed up when compared with the ARM implementation on the same chip. We present several strategies for different field sizes and field polynomials, and show that a 360MHz DSP easily outperforms the 500MHz ARM.
|
| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
Thesis.pdf |
2.47 Mb |
00:11:25 |
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