Title page for ETD etd-06252000-22510045


Type of Document Master's Thesis
Author Aust, Carrie Ellen
Author's Email Address caust@vt.edu
URN etd-06252000-22510045
Title A Low-Power, Variable-Resolution Analog-to-Digital Converter
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Member
Ha, Dong Sam Committee Member
Reed, Jeffrey Hugh Committee Member
Keywords
  • Analog-to-digital converter
  • ADC
  • Low power
  • Variable resolution
Date of Defense 2000-06-16
Availability unrestricted
Abstract
Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wireless digital communications systems is to detect the current channel condition and to dynamically vary the resolution of the ADC according to the given channel condition. In this thesis, we investigated an ADC that can change its resolution dynamically and, consequently, its power dissipation. Our ADC is a switched-current, redundant signed-digit (RSD) cyclic implementation that easily incorporates variable resolution. Furthermore, the RSD cyclic algorithm is insensitive to offsets, allowing simple, low-power comparators. Our ADC is implemented in a 0.35 um CMOS technology with a single-ended 3.3 V power supply. Our ADC has a maximum power dissipation of 6.35 mW for a 12-bit resolution and dissipates an average of 10 percent less power when the resolution is decreased by two bits. Simulation results indicate our ADC achieves a bit rate of 1.7 MHz and has a SNR of 84 dB for the maximum input frequency of 8.3 kHz.
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