Type of Document	Master's Thesis
Author	Adhipathi, Pradeep
URN	etd-06252004-201429
Title	Model based approach to Hardware/ Software Partitioning of SOC Designs
Degree	Master of Science
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Dr. James M. Baker Committee Chair Dr. F. Gail Gray Committee Member Dr. James R. Armstrong Committee Member
Keywords	hardware modeling partitioning system on chip co-design
Date of Defense	2004-06-21
Availability	unrestricted
Abstract As the IT industry marks a paradigm shift from the traditional system design model to System-On-Chip (SOC) design, the design of custom hardware, embedded processors and associated software have become very tightly coupled. Any change in the implementation of one of the components affects the design of other components and, in turn, the performance of the system. This has led to an integrated design approach known as hardware/software co-design and co-verification. The conventional techniques for co-design favor partitioning the system into hardware and software components at an early stage of the design and then iteratively refining it until a good solution is found. This method is expensive and time consuming. A more modern approach is to model the whole system and rigorously test and refine it before the partitioning is done. The key to this method is the ability to model and simulate the entire system. The advent of new System Level Modeling Languages (SLML), like SystemC, has made this possible. This research proposes a strategy to automate the process of partitioning a system model after it has been simulated and verified. The partitioning idea is based on systems modeled using Process Model Graphs (PmG). It is possible to extract a PmG directly from a SLML like SystemC. The PmG is then annotated with additional attributes like IO delay and rate of activation. A complexity heuristic is generated from this information, which is then used by a greedy algorithm to partition the graph into different architectures. Further, a command line tool has been developed that can process textually represented PmGs and partition them based on this approach.
Files	Filename       Size       Approximate Download Time (Hours:Minutes:Seconds)     28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access    thesis.pdf 298.99 Kb 00:01:23 00:00:42 00:00:37 00:00:18 00:00:01

If you have questions or technical problems, please Contact DLA.