Type of Document	Master's Thesis
Author	Donglikar, Swapneel B
Author's Email Address	getswapnil@gmail.com
URN	etd-07132009-232205
Title	Design for Testability Techniques to Optimize VLSI Test Cost
Degree	Master of Science
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Hsiao, Michael S. Committee Chair Abbott, A. Lynn Committee Member Huang, Chao Committee Member
Keywords	Test Application Time Reduction Test Data Volume Reduction Random Access Scan Design for Test Illinois Scan
Date of Defense	2009-06-26
Availability	restricted
Abstract High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test data volume and test application time. The degree of test data volume reduction depends on the fault coverage achievable in the broadcast mode. However, the fault coverage achieved in the broadcast mode of ILS architecture depends on the actual configuration of individual scan chains, i.e., the number of chains and the mapping of the individual flip-flops of the circuit to the respective scan chain positions. Current methods for constructing scan chains in ILS are either ad-hoc or use test pattern information from an a-priori automatic test pattern generation (ATPG) run. In this thesis, we present novel low cost techniques to construct ILS scan configuration for a given design. These techniques efficiently utilize the circuit topology information and try to optimize the flip-flop assignment to a scan chain location without much compromise in the fault coverage in the broadcast mode. Thus, they eliminate the need of an a-priori ATPG run or any test set information. In addition, we also propose a new scan architecture which combines the broadcast mode of ILS and Random Access Scan architecture to enable further test volume reduction on and above effectively configured conventional ILS architecture using the aforementioned heuristics with reasonable area overhead. Experimental results on the ISCAS’89 benchmark circuits show that the proposed ILS configuration methods can achieve on an average 5% more fault coverage in the broadcast mode and on average 15% more test data volume and test application time reduction than existing methods. The proposed new architecture achieves, on an average, 9% and 33% additional test data volume and test application time reduction respectively on top of our proposed ILS configuration heuristics.
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