Type of Document Master's Thesis Author Subramanian, Visvanathan URN etd-07142003-153854 Title Configurable Architecture for System-Level Prototyping of High-Speed Embedded Wireless Communication Systems Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Tront, Joseph G. Committee Chair Bostian, Charles W. Committee Member Midkiff, Scott F. Committee Member Keywords
- Configurable Architecture
- Rapid Prototyping
- Communication System Design
Date of Defense 2003-01-13 Availability unrestricted AbstractBroadband wireless technologies have the potential to provide integrated data and multimedia services in several niche areas. There is a growing need to develop high-performance communication systems that can satisfy high-end data processing requirements inherent in these technologies. The speed and complexity of these systems necessitates designers to break away from traditional architectures and design methodologies. A more comprehensive and demanding design and verification process including both hardware and software is required. Field-programmable gate arrays (FPGA) offer an attractive alternative to the low efficiency of Digital Signal Processor (DSP) based systems and low flexibility of Application Specific Integrated Circuits(ASIC). The availability of high-density, high-performance field-programmable gate arrays with several capabilities, like embedded memory and advanced routing, together with the adaptability that they offer make them highly desirable for developing hardware prototypes of communication systems.
This thesis describes the development of a configurable architecture and FPGA-based design methodology used in the development of a Local Multipoint Distribution Service (LMDS) gateway for a disaster response network. The design of the gateway posed several challenges due to high data rates (120 Mbits/sec) and adaptive features like variable Forward Error Correction Coding and optional link-level retransmissions. The design decisions and simulation results of the verification process are discussed in detail. Finally, the aspects of testing and integration of the prototype in the overall system are discussed.
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