Title page for ETD etd-07142004-162634


Type of Document Master's Thesis
Author Hunter III, Jesse Everett
Author's Email Address jehunte3@vt.edu
URN etd-07142004-162634
Title A Device-Level FPGA Simulator
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Patterson, Cameron D. Committee Member
Tront, Joseph G. Committee Member
Keywords
  • FPGA
  • Device Simulator
  • JHDLBits
  • JHDL
  • JBits
  • VTsim
  • Virtex-II
  • Xilinx
Date of Defense 2004-06-10
Availability unrestricted
Abstract
In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain support. Utilizing JBits3 and ADB, VTsim enables simulation and examination of all resources within an FPGA via a virtual device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction.
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