Title page for ETD etd-07172000-11270030


Type of Document Master's Thesis
Author Puckett, W. Bruce
Author's Email Address wipucket@vt.edu
URN etd-07172000-11270030
Title Implementation and Performance of an Improved Turbo Decoder on a Configurable Computing Machine
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Woerner, Brain D. Committee Chair
Athanas, Peter M. Committee Member
Tranter, William H. Committee Member
Keywords
  • Turbo Codes
  • SLAAC1V
  • FPGA
  • Wildforce
Date of Defense 2000-07-08
Availability unrestricted
Abstract
Turbo codes are a recently discovered class of error correction codes that achieve near-Shannon limit performance. Because of their complexity and highly parallel nature, turbo-coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform. The design's performance and throughput are emphasized in light of its algorithmic improvements, and its flexibility is emphasized as it is ported to a newer, more efficient architecture with more hardware resources. Because this decoder will eventually become the error correction component of a software radio, the design must maintain a high data rate, interface easily with other modules, and conserve hardware resources for future research developments.
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