Title page for ETD etd-07222000-13030026


Type of Document Master's Thesis
Author Ding, Zhimei
Author's Email Address zding@vt.edu
URN etd-07222000-13030026
Title Image Wavelet Compression Implementation Using a Run-Time Reconfigurable Custom Computing Machine
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Athanas, Peter M. Committee Chair
Jones, Mark T. Committee Member
Midkiff, Scott F. Committee Member
Keywords
  • FPGA RTRC CCM
Date of Defense 2000-06-14
Availability unrestricted
Abstract
This thesis presents the design and implementation of the Image Wavelet Compression (IWC) algorithm on Field Programmable Gate Arrays (FPGAs) by using the run-time reconfigurable custom computing machine design tool Janus. The four routines implementing the IWC are discussed. The structure of Janus is introduced and the IWC implementation design framework to use Janus structure is described in detail. The Janus hardware circuit design model, which has been used in the IWC implementation, is demonstrated here. The hardware implementation results are presented and analyzed, focusing on reconfiguration and computing time. Future research areas are suggested to improve the Janus tool.
Files
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