Title page for ETD etd-07232001-201851


Type of Document Dissertation
Author Srikanteswara, Srikathyayani
Author's Email Address swradio@vt.edu
URN etd-07232001-201851
Title Design and Implementation of a Soft Radio Architecture for Reconfigurable Platforms
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Reed, Jeffrey Hugh Committee Chair
Athanas, Peter M. Committee Member
Nance, Richard E. Committee Member
Tranter, William H. Committee Member
Woerner, Brian D. Committee Member
Keywords
  • Software Radio
  • SDR
  • Reconfigurable Computing
  • 3G Systems
  • Software Radio Architecture
  • Soft Radio
Date of Defense 2001-07-06
Availability unrestricted
Abstract
Software radios have evolved as multimode, programmable digital radios that perform radio functions using digital signal processing algorithms. They have been designed as software programmable radios using a combination of various hardware elements and structures. In this dissertation a {em{soft radio}} refers to a completely configurable radio that can be programmed through software, to change the radio behavior including the hardware functionality. Conventional software radios achieve flexibility through software with the use of static hardware. While these radios have the flexibility to operate in multiple modes, the hardware is not used efficiently. This inefficient utilization of hardware frequently limits the flexibility of software radios and the number of modes the radio can support. Soft radios however, attempt to gain flexibility through the use of reconfigurable hardware. The same piece of hardware can be configured to perform different functions based on the mode the radio is operating in.

While many soft/software radio architectures have been suggested and implemented, there remains a lack of a formal design methodology that can be used to design and implement reconfigurable soft radios. Most designs are based on ad hoc approaches which are appropriate only for the problem at hand.

After examining the design issues of a soft radio an architecture, called the {em{Layered Radio Architecture}}, is developed with the use of stream based processing and run-time reconfigurable hardware. These choices aid in maximizing performance with minimum hardware while keeping the architecture robust, simple, and scalable. The reconfigurable platform enables {em hardware paging} through reusability hardware. The stream-based approach gives a uniform modular structure to the processing modules and defines the protocol for interaction between various modules. The architecture describes a formal yet open design methodology and makes it possible to incorporate all of the features of a software radio while minimizing complexity issues. The layered architecture also defines the methodology for incorporating changes and updates into the system.

The layered radio architecture assumes run-time reconfigurability of the hardware. This feature is not supported by existing commercial reconfigurable hardware, like FPGAs. An Custom Computing Machine (CCM), called Stallion that supports fast run time reconfiguration, has been developed at Virginia Tech. This dissertation describes the deficiencies of existing commercial reconfigurable hardware and shows how the Stallion is capable of supporting the layered radio architecture.

The dissertation presents algorithms and procedures that can be used to implement the layered radio architecture using existing hardware. The architecture is validated with the implementation of two receivers: A single user CDMA receiver based on complex adaptive filtering and a W-CDMA downlink rake receiver with channel estimation. Performance analysis of these receivers show that it is important to keep the paging ratio high while maximizing utilization of the processing elements. The layered radio architecture with the use of Stallion can support existing high data rate systems.

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