Title page for ETD etd-07262010-183257


Type of Document Master's Thesis
Author Narayanaswamy, Ramya Priyadharshini
Author's Email Address ramya85@vt.edu
URN etd-07262010-183257
Title Design of a Power-aware Dataflow Processor Architecture
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jones, Mark T. Committee Chair
Martin, Thomas L. Committee Co-Chair
Plassmann, Paul E. Committee Member
Keywords
  • UPF
  • E-textiles
  • Dataflow
  • Power-aware
Date of Defense 2010-07-20
Availability unrestricted
Abstract
In a sensor monitoring embedded computing environment, the data from a sensor is an event that triggers the execution of an application. A sensor node consists of multiple sensors and a general purpose processor that handles the multiple events by deploying an event-driven software model. The software overheads of the general purpose processors results in energy inefficiency. What is needed is a class of special purpose processing elements which are more energy efficient for the purpose of computation. In the past, special purpose microcontrollers have been designed which are energy efficient for the targeted application space. However, reuse of the same design techniques is not feasible for other application domains. Therefore, this thesis presents a power-aware dataflow processor architecture targeted for the electronic textile computing space. The processor architecture has no instructions, and handles multiple events inherently without deploying software methods. This thesis also shows that the power-aware implementation reduces the overall static power consumption.
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