Title page for ETD etd-08102011-151100


Type of Document Master's Thesis
Author Sinha, Ambuj Sudhir
Author's Email Address ambujs87@vt.edu
URN etd-08102011-151100
Title Design Techniques for Side-channel Resistant Embedded Software
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Schaumont, Patrick Robert Committee Chair
Hsiao, Michael S. Committee Member
Shukla, Sandeep K. Committee Member
Keywords
  • Bitslice Cryptography
  • Side Channel Attacks
  • Virtual Secure Circuit
  • Secure Embedded Systems
  • Side-channel Countermeasures
Date of Defense 2011-08-05
Availability unrestricted
Abstract
Side Channel Attacks (SCA) are a class of passive attacks on cryptosystems that exploit implementation characteristics of the system. Currently, a lot of research is focussed towards developing countermeasures to side channel attacks. In this thesis, we address two challenges that are an inherent part of the efficient implementation of SCA countermeasures. While designing a system, design choices made for enhancing the efficiency or performance of the system can also affect the side channel security of the system. The first challenge is that the effect of different design choices on the side channel resistance of a system is currently not well understood. It is important to understand these effects in order to develop systems that are both secure and efficient. A second problem with incorporating SCA countermeasures is the increased design complexity. It is often difficult and time consuming to integrate an SCA countermeasure in a larger system.

In this thesis, we explore that above mentioned problems from the point of view of developing embedded software that is resistant to power based side channel attacks. Our first work is an evaluation of different software AES implementations, from the perspective of side channel resistance, that shows the effect of design choices on the security and performance of the implementation. Next we present work that identifies the problems that arise while designing software for a particular type of SCA resistant architecture - the Virtual Secure Circuit. We provide a solution in terms of a methodology that can be used for developing software for such a system - and also demonstrate that this methodology can be conveniently automated - leading to swifter and easier software development for side channel resistant designs.

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