Title page for ETD etd-08112012-013904


Type of Document Master's Thesis
Author Mandlekar, Anup Shrikant
URN etd-08112012-013904
Title An Application Framework for a Power-Aware Processor Architecture
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jones, Mark T. Committee Chair
Martin, Thomas L. Committee Member
Plassmann, Paul E. Committee Member
Keywords
  • Low Power Flash Memory Cells
  • Model Driven Engineering
  • Simulink
  • Dataflow Architecture
Date of Defense 2012-08-07
Availability unrestricted
Abstract
The instruction-set based general purpose processors are not energy-efficient for event-driven applications. The E-textiles group at Virginia Tech proposed a novel data-flow processor architecture design to bridge the gap between event-driven applications and the target architecture. The architecture, although promising in terms of performance and energy-efficiency,

was explored for limited number of applications. This thesis presents a model-driven approach for the design of an application framework, facilitating rapid development of software

applications to test the architecture performance. The application framework is integrated

with the prior automation framework bringing software applications at the right level of abstraction. The processor architecture design is made flexible and scalable, making it suitable

for a wide range of applications. Additionally, an embedded flash memory based architecture design for reduction in the static power consumption is proposed. This thesis estimates significant reduction in overall power consumption with the incorporation of flash memory.

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