Title page for ETD etd-08122010-161305


Type of Document Master's Thesis
Author Chandrasekharan, Athira
Author's Email Address athira@vt.edu
URN etd-08122010-161305
Title Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Patterson, Cameron D. Committee Chair
Athanas, Peter M. Committee Member
Plassmann, Paul E. Committee Member
Keywords
  • Reconfigurable Computing
  • Incremental Floorplanning
  • FPGAs
Date of Defense 2010-08-05
Availability unrestricted
Abstract
FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or quality of results. We approach the problem in a different way for development environments in which some circuit speed and area optimization may be sacrificed for improved implementation and debug turnaround. The PATIS floorplanner enables dynamic modular design, which accelerates non-local changes to the physical layout arising from design exploration and the addition of debug circuitry. We focus in this work on incremental and speculative floorplanning in PATIS, to accommodate minor design changes and to proactively generate possible floorplan variants. Current floorplan topology is preserved to minimize ripple effects and maintain reasonable module aspect ratios. The design modules are run-time reconfigurable to enable concurrent module implementation by independent invocations of the standard FPGA tools running on separate cores or hosts.
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