Title page for ETD etd-08152006-185857


Type of Document Master's Thesis
Author Billian, Bruce
URN etd-08152006-185857
Title Next Generation Design of a Frequency Data Recorder Using Field Programmable Gate Arrays
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Liu, Yilu Committee Chair
Conners, Richard W. Committee Member
Nelson, Douglas J. Committee Member
Keywords
  • Frequency Disturbance Recorder
  • FDR
  • FNET
  • Field Programmable Gate Array
  • FPGA
  • Frequency Monitoring Network
  • Time Synchronization
  • Power System Monitoring
Date of Defense 2005-05-10
Availability unrestricted
Abstract

The Frequency Disturbance Recorder (FDR) is a specialized data acquisition device designed to monitor fluctuations in the overall power system. The device is designed such that it can be attached by way of a standard wall power outlet to the power system. These devices then transmit their calculated frequency data through the public internet to a centralized data management and storage server.

By distributing a number of these identical systems throughout the three major North American power systems, Virginia Tech has created a Frequency Monitoring Network (FNET). The FNET is composed of these distributed FDRs as well as an Information Management Server (IMS). Since frequency information can be used in many areas of power system analysis, operation and control, there are a great number of end uses for the information provided by the FNET system. The data provides researchers and other users with the information to make frequency analyses and comparisons for the overall power system. Prior to the end of 2004, the FNET system was made a reality, and a number of FDRs were placed strategically throughout the United States.

The purpose of this thesis is to present the elements of a new generation of FDR hardware design. These elements will enable the design to be more flexible and to lower reliance on some vendor specific components. Additionally, these enhancements will offload most of the computational processing required of the system to a commodity PC rather than an embedded system solution that is costly in both development time and financial cost. These goals will be accomplished by using a Field Programmable Gate Array (FPGA), a commodity off-the-shelf personal computer, and a new overall system design.

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