Title page for ETD etd-08192010-185505


Type of Document Master's Thesis
Author Lakshminarayana, Avinash
Author's Email Address avinashl@vt.edu
URN etd-08192010-185505
Title Evaluation Techniques for Mapping IPs on FPGAs
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Shukla, Sandeep K. Committee Chair
Ha, Dong Sam Committee Member
Schaumont, Patrick Robert Committee Member
Keywords
  • Regression Analysis
  • Pareto Optimization
  • Power Estimation
  • Prototyping
  • High Level Synthesis
  • Design Space Exploration
Date of Defense 2010-08-11
Availability unrestricted
Abstract
The phenomenal density growth in semiconductors has resulted in the availability of billions

of transistors on a single die. The time-to-design is shrinking continuously due to aggressive

competition. Also, the integration of many discrete components on a single chip is growing

at a rapid pace. Designing such heterogeneous systems in short duration is becoming difficult

with existing technology. Field-Programmable Gate Arrays offer a good alternative in both

productivity and heterogeneity issues. However, there are many obstacles that need to be

addressed to make them a viable option. One such obstacle is the lack of early design space

exploration tools and techniques for FPGA designs. This thesis develops techniques to evaluate

systematically, the available design options before the actual system implementation.

The aspect which makes this problem interesting, yet complicated, is that a system-level

optimization is not linearly summable. The discrete components of a system, benchmarked

as best in all design parameters — speed, area and power, need not add up to the best

possible system. This work addresses the problem in two ways. In the first approach,

we demonstrate that by working at higher levels of abstraction, one can achieve orders of

improvement in productivity. Designing a system directly from its behavioral description is

an on-going effort in industry. Instead of focusing on design aspects, we use these methods to

develop quick prototypes and estimate the design parameters. Design space exploration needs

relative comparison among available choices and not accurate values of design parameters.

It is shown that the proposed method can do an acceptable job in this regard. The second

approach is about evolving statistical techniques for estimating the design parameters and

then algorithmically searching the design space. Specifically, a high level power estimation

model is developed for FPGA designs. While existing techniques develop power model for

discrete components separately, this work evaluates the option of generic power model for

multiple components.

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