Type of Document	Master's Thesis
Author	Zhao, Jun
Author's Email Address	juzhao@vt.edu
URN	etd-08222002-152733
Title	Development of Integrated "Chip-Scale" Active Antennas for Wireless Applications
Degree	Master of Science
Department	Electrical and Computer Engineering
Advisory Committee	Advisor Name Title Raman, Sanjay Committee Chair Stutzman, Warren L. Committee Member Sweeney, Dennis G. Committee Member
Keywords	Microstrip antenna power amplifier integrated antenna
Date of Defense	2002-07-26
Availability	unrestricted
Abstract With the rapid expansion of wireless communication services, ultra-miniature, low cost RF microsystems operating at higher carrier frequencies (e.g. 5-6 GHz) are in demand for various applications. Such applications include networked wireless sensor nodes and wireless local area data networks (WLANs). Integrated microstrip antennas coupled directly to the RF electronics, offer potential advantages of low cost, reduced parasitics, simplified assembly and design flexibility compared to systems based on discrete antennas. However, the size of such antennas is governed by physical laws, and cannot be arbitrarily reduced. The critical patch antenna dimension at resonance needs to be ~λg/2 (where λg is the guided wavelength given by λg =λ/sqrt(er) . Several methods are available to reduce the physical size of the antenna to enable on-chip integration. A high dielectric constant substrate reduces the guided wavelength. Grounding one edge of the microstrip patch enables the resonant antenna length to be further reduced to ~λg/4. However, these techniques result in degraded antenna efficiency and bandwidth. Nonetheless, such antennas still have potential for use in low power/short range applications. In this work, "electrically small" (small with respect to λo) square-shaped microstrip patch antennas, grounded on one edge by shorting posts, have been investigated. The antenna input impedance depends on the feed position; by adjusting the feed point, the antenna can be tuned to match a 50 Ω or other system impedance. The antennas were designed on a GaAs substrate, with a high dielectric constant of 12.9. The size of the patch antenna is further reduced by utilizing shorted through substrate vias along one edge. The size of the antenna is about 4.2mm × 4.2mm, which is ~1/13 of λo at ~5.6GHz. The antennas are practical for integration on chip. Due to the size reduction, the simulated peak gain of the antenna is only −10.2 dB ( ~3.2% radiation efficiency). However, this may be acceptable for short-range wireless communications and distributed sensor network applications. Based on the above approach, integrated GaAs "chip-scale" antennas with matching power amplifiers have been designed and fabricated. Class A tuned MESFET power amplifiers (PAs) were designed with outputs directly matched to the antenna feed point. The antenna is fabricated on the backside of the chip through backside patterning; the PA feeds the antenna through a backside via. The structure is then mounted such that the antenna faces up, and is compatible with flip-chip technology. The measurement of a 50 Ω passive (no PA) antenna indicates a gain of -12.7dB on boresight at 5.64 GHz, consistent with the antenna size reduction. The measurement of one active antenna (50 Ω system) shows a gain of -4.3dB on boresight at 5.80 GHz. The other version of active antenna (22.5 Ωsystem) shows a gain of -2.9 dBi on boresight at 5.725 GHz. The active circuitry (PA) contributes an average of ~9 dB gain in the active antenna, reasonable close to the designed PA gain of 12.7dB. The feasibility of direct integration of a PA with an on-chip antenna in a commercial GaAs process at RF frequencies was successfully demonstrated.
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