Title page for ETD etd-08292008-063326


Type of Document Master's Thesis
Author Vuppala, Srilekha
URN etd-08292008-063326
Title Methodology for VHDL performance model construction and validation
Degree Master of Science
Department Electrical Engineering
Advisory Committee
Advisor Name Title
No Advisors Found
Keywords
  • VHDL
  • performance modeling
  • model construction
  • model validation
Date of Defense 1996-00-00
Availability restricted
Abstract
Files
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[VT] LD5655.V855_1996.V877.pdf 4.11 Mb 00:19:01 00:09:46 00:08:33 00:04:16 00:00:21
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