Title page for ETD etd-08302000-21580051


Type of Document Master's Thesis
Author Sulistyo, Jos Budi
Author's Email Address jsulisty@ee.vt.edu
URN etd-08302000-21580051
Title On the Characterization of Library Cells
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Ha, Dong Sam Committee Chair
Armstrong, James R. Committee Member
Gray, Festus Gail Committee Member
Keywords
  • VLSI
  • Cadence
  • Characterization
  • Synopsys
  • Timing Model
  • Power Estimation
  • Standard Cell
Date of Defense 2000-08-18
Availability unrestricted
Abstract
In this work, a simplified method for performing characterization of a standard cell is presented. The method presented here is based on Synopsys models of cell delay and power dissipation, in particular the linear delay model. This model is chosen as it allows rapid characterization with a modest number of simulations, while still achieving acceptable accuracy. Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a dual 4-bit counter, was built using the library to demonstrate the suitability of the method.
Files
  Filename       Size       Approximate Download Time (Hours:Minutes:Seconds) 
 
 28.8 Modem   56K Modem   ISDN (64 Kb)   ISDN (128 Kb)   Higher-speed Access 
  thesis.pdf 1.46 Mb 00:06:46 00:03:29 00:03:03 00:01:31 00:00:07

Browse All Available ETDs by ( Author | Department )

dla home
etds imagebase journals news ereserve special collections
virgnia tech home contact dla university libraries

If you have questions or technical problems, please Contact DLA.