| Type of Document |
Master's Thesis |
| Author |
Davies, John Clay
|
| URN |
etd-08312000-15590002 |
| Title |
Design and Implementation of an FPGA-based Soft-Radio Receiver Utilizing Adaptive Tracking
|
| Degree |
Master of Science |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Peter Athanas |
Committee Chair |
| Jeffrey Reed |
Committee Member |
| Timothy Pratt |
Committee Member |
|
| Keywords |
- Adaptive Receiver
- Adaptive Tracking
- Software Radio
- CDMA
- Configurable Computing
- FPGA
|
| Date of Defense |
2000-08-25 |
| Availability |
unrestricted |
Abstract
The wireless market of the future will demand inexpensive hardware, expandability, interoperability, and the implementation of advanced signal processing functions—-i.e. a software radio. Configurable computing machines are often ideal software radio platforms. In particular, the Stallion reconfigurable processor’s efficient hardware reuse and scalability fulfill these radio’s demands. The advantages of Stallion-based design inspired an FPGA-based software radio—the proto-Stallion receiver. This thesis introduces the proto-Stallion architecture and details its implementation on the SLAAC-1V FPGA platform. Although this thesis presents a specific radio implementation, this architecture is flexible; it can support a variety of applications within its fixed framework. This implemented single-user DS-CDMA receiver utilizes an LMS adaptive filter that can combat MAI and constructively combine multipath; most notably, this receiver employs an adaptive tracking algorithm that harnesses the LMS algorithm to maintain symbol synchronization. The proto-Stallion receiver demonstrates the dependence of adaptive tracking on channel noise; the algorithm requires significant noise levels to maintain synchronization.
|
| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
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jcd4_thesis.pdf |
257.35 Kb |
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