| Type of Document |
Master's Thesis |
| Author |
Steiner, Neil Joseph
|
| URN |
etd-09112002-143335 |
| Title |
A Standalone Wire Database for Routing and Tracing in Xilinx Virtex, Virtex-E, and Virtex-II FPGAs |
| Degree |
Master of Science |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Athanas, Peter M. |
Committee Chair |
| Cyre, Walling R. |
Committee Member |
| Jones, Mark T. |
Committee Member |
| Patterson, Cameron D. |
Committee Member |
|
| Keywords |
- Virtex
- FPGA
- Xilinx
- ADB
- Alternate Wire Database
|
| Date of Defense |
2002-08-30 |
| Availability |
unrestricted |
Abstract
Modern FPGAs contain routing resources easily exceeding millions of wires. While mainstream design flows and place-and-route tools make very good use of these routing resources, they do so at the cost of very significant processing time. A well established alternative scheme is to modify or generate configuration bitstreams directly, resulting in more dynamic designs and shorter processing times. This thesis introduces a complete set of alternate wire databases for Xilinx Virtex, Virtex-E, and Virtex-II FPGAs, suitable for standalone use or as an addition to the JBits API. The databases can be used to route or trace through any device in these families, and can generate the necessary bitstream configurations with the help of JBits or an independent bitstream interface.
|
| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
thesis.pdf |
1.14 Mb |
00:05:15 |
00:02:42 |
00:02:21 |
00:01:10 |
00:00:06 |
|
