Type of Document Master's Thesis Author Saha, Sonal Author's Email Address sonal3@vt.edu URN etd-09122011-125316 Title An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Ravindran, Binoy Committee Chair Broadwater, Robert P. Committee Member Plassmann, Paul E. Committee Member Keywords
- Dynamic Voltage and Frequency Scaling
- Real-Time Linux
Date of Defense 2011-09-09 Availability unrestricted Abstract Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage-ment technique, which aims to reduce the energy consumption of computing platforms by
dynamically scaling the CPU frequency. Real-Time DVFS (RT-DVFS) is a branch of DVFS,
which reduces CPU energy consumption through DVFS, while at the same time ensures that
task time constraints are satisfied by constructing appropriate real-time task schedules. The
literature presents numerous RT-DVFS scheduling algorithms, which employ different tech-
niques to utilize the CPU idle time to scale the frequency. Many of these algorithms have
been experimentally studied through simulations, but have not been implemented on real
hardware platforms. Though simulation-based experimental studies can provide a first-order
understanding, implementation-based studies can reveal actual timeliness and energy con-
sumption behaviours. This is particularly important, when it is difficult to devise accurate
simulation models of hardware, which is increasingly the case with modern systems.
In this thesis, we study the timeliness and energy consumption behaviours of fourteen state-
of-the-art RT-DVFS schedulers by implementing and evaluating them on two hardware plat-
forms. The schedulers include CC-EDF, LA-EDF, REUA, DRA andd AGR1 among others,
and the hardware platforms include ASUS laptop with the Intel I5 processor and a mother-
board with the AMD Zacate processor. We implemented these schedulers in the ChronOS
real-time Linux kernel and measured their actual timeliness and energy behaviours under
a range of workloads including CPU-intensive, memory-intensive, mutual exclusion lock-
intensive, and processor-underloaded and overloaded workloads.
Our studies reveal that measuring the CPU power consumption as the cube of CPU fre-
quency can lead to incorrect conclusions. In particular, it ignores the idle state CPU power
consumption, which is orders of magnitude smaller than the active power consumption.
Consequently, power savings obtained by exclusively optimizing active power consumption
(i.e., RT-DVFS) may be offset by completing tasks sooner by running them at the highest
frequency and transitioning to the idle state earlier (i.e., no DVFS). Thus, the active power
consumption savings of the RT-DVFS techniques’ that we report are orders of magnitude
smaller than their simulation-based savings reported in the literature.
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