Type of Document Master's Thesis Author Benz, Matthew Aaron Author's Email Address email@example.com URN etd-09132007-045308 Title A Cross Platform Method for FPGA Integrity Checking Degree Master of Science Department Electrical and Computer Engineering Advisory Committee
Advisor Name Title Jones, Mark T. Committee Chair Athanas, Peter M. Committee Member Patterson, Cameron D. Committee Member Keywords
Date of Defense 2007-08-30 Availability unrestricted AbstractAs embedded systems continue to evolve and the number of applications they support continues to increase, so does the diversity of the hardware they employ. As a result, the
Field Programmable Gate Arrays (FPGAs), which have become fundamental elements in their design, have advanced in size and complexity as well. Because of this, it is now impossible to ignore the security implications that accompany such a progression. It is then not only important to prevent malicious attacks targeted at FPGAs from extracting the intellectual property contained in their configuration, but to now extend the research in this field by providing a cross-platform solution capable of securing the integrity of FPGA configurations at run-time. Today, there exist myriad attack strategies employed against FPGAs, the majority of which are seen in the form of semi-invasive attacks. These attacks manipulate the configuration of an FPGA and typically modify the state of the transistors that make up said configuration.
This thesis introduces a multi-platform method for checking the integrity of an FPGA’s configuration. The details of the system’s design and implementation are discussed in addition to the analysis of the design trade-offs met when employing the system across multiple FPGA families. The system is implemented entirely in hardware and resides on-chip, providing an FPGA the ability to act as private entity capable of successfully detecting when it has been maliciously attacked.
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