| Type of Document |
Master's Thesis |
| Author |
Hess, Jason Richard
|
| Author's Email Address |
jhess@vt.edu |
| URN |
etd-092099-142008 |
| Title |
Implementation of a Turbo Decoder on a Configurable Computing Platform |
| Degree |
Master of Science |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Athanas, Peter M. |
Committee Chair |
| Jones, Mark T. |
Committee Member |
| Reed, Jeffrey Hugh |
Committee Member |
|
| Keywords |
- configurable computing
- FPGA
- turbo codes
|
| Date of Defense |
1999-09-17 |
| Availability |
unrestricted |
Abstract
Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs.
This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasized in the implementation so that the decoder can be used as part of a configurable software radio. The system presented performs turbo decoding for a variable block size with a variable number of decoding iterations while using only a single FPGA. When six iterations are performed, the decoder operates at an information bit rate greater than 32 kbps.
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| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
etd.pdf |
469.15 Kb |
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