Title page for ETD etd-09232008-144806


Type of Document Dissertation
Author Li, Wencheng
URN etd-09232008-144806
Title A test generation system for behaviorally modeled digital circuits
Degree PhD
Department Electrical Engineering
Advisory Committee
Advisor Name Title
No Advisors Found
Keywords
  • VHDL models
Date of Defense 1996-06-15
Availability restricted
Abstract

This dissertation presents an approach to generating tests from a VHDL behavioral model. The tests can be used to thoroughly exercise the VHDL model and detect the faults in the equivalent gate level circuit of the model. The VHDL model is developed with the help of the Modeler's Assistant and represented as a Process Model Graph (PMG). A set of VHDL functions have been constructed to help develop VHDL models. Two algorithms are proposed to implement the test generation. P-Algorithm is used to generate tests at the process level. For each process a symbolic test set and the corresponding fixed valued test packages (FVTPs) are generated. Synthesis-related FVTP generation algorithms for the VHDL functions are derived to support the P-algorithm. E-Algorithm is employed to generate the entity level tests. The symbolic entity level tests are generated first and then the final fixed valued entity level tests are obtained by calculating the symbolic expressions. The Synopsys synthesis tools are used to get the equivalent gate level circuit of a VHDL model. The HILO fault grader is used to generate fault coverage. Several conversion programs have been developed to support the test evaluation.

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