Title page for ETD etd-09272006-114810


Type of Document Master's Thesis
Author Webb, James Braxton
Author's Email Address jawebb4@vt.edu
URN etd-09272006-114810
Title Methods for Securing the Integrity of FPGA Configurations
Degree Master of Science
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jones, Mark T. Committee Chair
Athanas, Peter M. Committee Member
Patterson, Cameron D. Committee Member
Keywords
  • authentication
  • integrity
  • fault-injection
  • embedded system
  • reconfigurable
  • dynamic
  • partial
  • security
  • FPGA
  • configuration
  • configurable
Date of Defense 2006-08-29
Availability unrestricted
Abstract
As Field Programmable Gate Arrays (FPGAs) continue to become integral parts of embedded systems, it is imperative to consider their security. While much of the research in this field is oriented toward the protection of the intellectual property contained in the FPGA's configuration, the protection of the design's integrity from malicious attack against the configuration is critical to the operation of the system. Methods for attacking the configuration are semi-invasive attacks, such as fault injection, and data tampering of incoming partial bitstreams.

This thesis introduces methods for securing the integrity of an FPGA's configuration. The design and implementation is discussed for a system that consists of three parts. The first subsystem monitors the running configuration. The second subsystem authenticates partial bistreams that may be used for repairing the configuration from malicious alterations during run-time. The third subsystem indicates if the system itself succumbs to a malicious attack. The system is implemented on-chip, allowing the FPGA to effectively secure itself from attack.

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