| Type of Document |
Dissertation |
| Author |
Frangieh, Tannous
|
| Author's Email Address |
tannous@vt.edu |
| URN |
etd-10082012-021855 |
| Title |
A Design Assembly Technique for FPGA Back-End Acceleration |
| Degree |
PhD |
| Department |
Electrical and Computer Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Athanas, Peter M. |
Committee Chair |
| Dietrich, Carl B. |
Committee Member |
| Feng, Wu-Chun |
Committee Member |
| Nelson, Brent E. |
Committee Member |
| Schaumont, Patrick Robert |
Committee Member |
|
| Keywords |
- Configurable Computing
- FPGA Productivity
- Design Assembly Flow
- Electronic Design Automation
- Design Reuse
|
| Date of Defense |
2012-09-28 |
| Availability |
unrestricted |
Abstract
Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.
|
| Files |
| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
|
| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
| |
Frangieh_T_D_2012.pdf |
2.39 Mb |
00:11:03 |
00:05:41 |
00:04:58 |
00:02:29 |
00:00:12 |
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