Title page for ETD etd-10112006-204811


Type of Document Dissertation
Author Edmison, Joshua Nathaniel
URN etd-10112006-204811
Title Hardware Architectures for Software Security
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Jones, Mark T. Committee Chair
Abbott, A. Lynn Committee Member
Athanas, Peter M. Committee Member
Brown, Ezra A. Committee Member
Martin, Thomas L. Committee Member
Patterson, Cameron D. Committee Member
Keywords
  • security
  • information flow
  • architecture
  • FPGA
  • configurable
  • graph theory
Date of Defense 2006-06-30
Availability unrestricted
Abstract
The need for hardware-based software protection stems primarily from the increasing value of software coupled with the inability to trust software that utilizes or manages shared resources. By correctly utilizing security functions in hardware, trust can be removed from software.

Existing hardware-based software protection solutions generally suffer from utilization of trusted software, lack of implementation, and/or extreme measures such as processor redesign. In contrast, the research outlined in this document proposes that substantial, hardware-based software protection can be achieved, without trusting software or redesigning the processor, by augmenting existing processors with security management hardware placed outside of the processor boundary. Benefits of this approach include the ability to add security features to nearly any processor, update security features without redesigning the processor, and provide maximum transparency to the software development and distribution processes. The major contributions of this research include the the augmentation methodology, design principles, and a graph-based method for analyzing hardware-based security systems.

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