Title page for ETD etd-11062000-08510043


Type of Document Dissertation
Author Ye, Zhihong
Author's Email Address zhye@vt.edu
URN etd-11062000-08510043
Title Modeling and Control of Parallel Three-Phase PWM Converters
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Boroyevich, Dushan Committee Chair
Chen, Dan Y. Committee Member
Lai, Jason Committee Member
Lee, Fred C. Committee Member
Nayfeh, Ali H. Committee Member
Keywords
  • circulating current
  • common-mode noise
  • multi-phase converter
  • four-leg converter
  • PWM converters
  • zero-sequence
  • current-bidirectional
  • current-unidirectional
  • load sharing
  • parallel
  • three-phase
Date of Defense 2000-09-15
Availability unrestricted
Abstract
This dissertation studies modeling and control issues of parallel three-phase pulse-width modulated (PWM) converters. The converters include three-phase boost rectifiers, voltage source inverters, buck rectifiers and current source inverters.

The averaging of the parallel converters is performed based on a generic functional switching unit, which is called a phase leg in boost rectifiers and voltage source inverters, and a rail arm in buck rectifiers and current source inverters. Based on phase-leg and rail-arm averaging, the developed models are not only equivalent to the conventional three-phase converter models that are based on phase-to-phase averaging, but they also preserve common-mode information, which is critical in the analysis of the parallel converters. The models reveal such parallel dynamics as reactive power circulation and small-signal interaction.

A unique feature of the parallel three-phase converters is a zero-sequence circulating current. This work proposes a novel zero-sequence control concept that uses variable zero-vectors in the space-vector modulation (SVM) of the converters. The control can be implemented within an individual converter and is independent from the other control loops for the converter. Therefore, it greatly facilitates the design and expansion of a parallel system.

Proper operation of the parallel converters requires an explicit load-sharing mechanism. In order to have a modular design, a droop method is recommended. Traditionally, however, a droop method has to compromise between voltage regulation and load sharing. After parametric analysis, a novel droop method using a gain-scheduling technique is proposed. The numeric analysis shows that the proposed droop method can achieve both good voltage regulation and good load sharing.

An interleaving technique is often used in parallel converter systems in order to reduce current ripples. Because of its symmetrical circuit structure, the parallel three-phase converter system can reduce both differential-mode and common-mode noise with a center-aligned symmetrical SVM.

Based on the concept that a symmetrical circuit can reduce common-mode dv/dt noise, a conventional three-phase, four-leg inverter is modified so that its fourth leg is symmetrical to the other three legs. The common-mode dv/dt noise can be practically eliminated with a new modulation strategy. Meanwhile, with a modified control design, the new four-leg inverter still can handle low-frequency common-mode components that occur due to unbalanced and nonlinear load.

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  Chapter1.pdf 22.84 Kb 00:00:06 00:00:03 00:00:02 00:00:01 < 00:00:01
  Chapter2.pdf 3.22 Mb 00:14:53 00:07:39 00:06:42 00:03:21 00:00:17
  Chapter3.pdf 2.07 Mb 00:09:35 00:04:56 00:04:19 00:02:09 00:00:11
  Chapter4.pdf 318.44 Kb 00:01:28 00:00:45 00:00:39 00:00:19 00:00:01
  Chapter5.pdf 178.49 Kb 00:00:49 00:00:25 00:00:22 00:00:11 < 00:00:01
  Chapter6.pdf 76.93 Kb 00:00:21 00:00:10 00:00:09 00:00:04 < 00:00:01
  Chapter7.pdf 362.92 Kb 00:01:40 00:00:51 00:00:45 00:00:22 00:00:01
  Chapter8.pdf 9.41 Kb 00:00:02 00:00:01 00:00:01 < 00:00:01 < 00:00:01
  Frontpages.pdf 12.98 Kb 00:00:03 00:00:01 00:00:01 < 00:00:01 < 00:00:01
  References.pdf 26.42 Kb 00:00:07 00:00:03 00:00:03 00:00:01 < 00:00:01
  TOC.pdf 26.11 Kb 00:00:07 00:00:03 00:00:03 00:00:01 < 00:00:01
  Vita.pdf 2.69 Kb < 00:00:01 < 00:00:01 < 00:00:01 < 00:00:01 < 00:00:01

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