| Type of Document |
Master's Thesis |
| Author |
Adkar, Sanjay
|
| URN |
etd-11142012-040027 |
| Title |
A versatile I/O system for a real time image processor |
| Degree |
Master of Science |
| Department |
Electrical Engineering |
| Advisory Committee |
| Advisor Name |
Title |
| Nadler, Morton |
Committee Chair |
| Armstrong, James R. |
Committee Member |
| Tront, Joseph G. |
Committee Member |
|
| Keywords |
|
| Date of Defense |
1986-08-05 |
| Availability |
restricted |
Abstract
A versatile I/O system for a real time image processor and a
complex clocking circuit for the I/O system and the image
processor have been designed. The I/O system receives data
from an arbitrary video source. These data are digitized and
conditioned to be compatible with the image processor. The
image processor output is conditioned such that these data
can be displayed on a standard RS l7O 2:l video monitor.
Variable frame rate reduction. circuits and. bit reduction
techniques such as line, column and dot interlace are incorporated
during output conditioning. Experiments on reducing
the frame rate and bit rate of a processed image can be
carried out using this I/O system.
|
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| Filename |
Size |
Approximate Download Time
(Hours:Minutes:Seconds)
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| 28.8 Modem |
56K Modem |
ISDN (64 Kb) |
ISDN (128 Kb) |
Higher-speed Access |
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LD5655.V855_1986.A343.pdf |
6.23 Mb |
00:28:49 |
00:14:49 |
00:12:58 |
00:06:29 |
00:00:33 |
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