Title page for ETD etd-11192006-102013


Type of Document Dissertation
Author Collins, Gustina B
Author's Email Address gucollin@vt.edu
URN etd-11192006-102013
Title Design, Fabrication and Testing of Conformal, Localized Wafer-level Packaging for RF MEMS Devices
Degree PhD
Department Electrical and Computer Engineering
Advisory Committee
Advisor Name Title
Lu, Guo-Quan Committee Co-Chair
Raman, Sanjay Committee Co-Chair
Guido, Louis J. Committee Member
Hendricks, Robert W. Committee Member
Scales, Wayne A. Committee Member
Keywords
  • wafer-level packaging
  • RF MEMS
  • MEMS Packaging
  • monolithic packaging
  • hermetic packaging
  • eutectic bonding
Date of Defense 2006-06-05
Availability unrestricted
Abstract
A low-cost, low-temperature packaging concept is proposed for localized sealing and

control of the ambient of a device cavity appropriate for Radio-Frequency (RF) Micro-

Electro-Mechanical (MEMS) devices, such as resonators and switches. These devices

require application specific packaging to facilitate their integration, provide protection

from the environment, and control interactions with other circuitry. In order to inte-

grate these devices into standard integrated circuit (IC) process flows and minimize

damage due to post-fabrication steps, packaging is performed at the wafer level.

In this work Indium and Silver are used to seal a monolithic localized hermetic pack-

age. The cavity protecting the device is formed using standard lithography-based

processing techniques. Metal walls are built up from the substrate and encapsulated

by a glass or silicon lid to create a monolithic micro-hermetic package surrounding a

predefined RF microsystem. The bond for the seal is then formed by rapid alloying

of Indium and Silver using a temperature greater than that of the melting point of

Indium. This ensures that the seal formed can subsequently function at tempera-

tures higher than the melting temperature of pure Indium. This method offers a

low-temperature bonding technique with thermal robustness suitable for wafer-level

process integration. The ultimate goal is to create a seal in a vacuum environment.

In this dissertation, design trade-offs made in wafer-level packaging are explained

using thermo-mechanical stress and electrical performance simulations. Prototype

passive microwave circuits are packaged using the developed packaging process and

the performance of the fabricated circuits before and after packaging is analyzed. The

effect of the package on coplanar waveguide structures are characterized by measur-

ing scattering parameters and models are developed as a design tool for wafer-level

package integration. The small scale of the localized package is expected to provide

greater reliability over conventional full chip packages.

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